MIPS Single-Cycle Processor (Logisim)
Designed and implemented a 32-bit single-cycle MIPS
processor to understand CPU architecture and instruction
execution.
Supported instruction categories: arithmetic/logic
(add, sub, and, or, xor, slt, li), shift (sll, srl, sra), memory
(lw, sw), and control-flow (j, jr, jal, jalr, beq, bne).
Built core components: Program Counter, Instruction
Memory, Register File, ALU, Data Memory, Control Unit,
and ALU Control.
Implemented proper control signal generation for each
instruction type to manage instruction fetch, decode,
execute, memory access, and write-back stages.
Result: Achieved a functioning processor that
executes a broad set of MIPS instructions within a
single clock cycle.